In-line voltage contrast (VC) inspection is a powerful technique for detecting and isolating yield limiting defects in the semiconductor fabricating industry. In-line VC inspection includes scanning the wafer surface of a NFET device in which test structures exist with a scanning electron microscope (SEM). As the inspection proceeds, the SEM induces charge on all electrically floating elements whereas any grounded elements remain at zero potential. This potential difference is visible to the SEM.
Many key defect types may be detected because their existence changes the electrical nature of the electrical nodes they contact. Most of the key applications for VC inspection involve defects that dramatically change the grounding of these nodes. For instance, with a bulk silicon technology, under the typical electron extracting conditions, an open contact on the source or drain (S/D) of a PFET has 3 to 6 magnitudes less capacitance and leakage resistance than a good contact. That is because the good contact draws electrons from the P+S/D region as well as the N well underneath.
However, to date, VC contrast inspection has been much less effective for defects which only marginally change the capacitance and leakage resistance of the structure they reside on. For instance, consider a contact on SOI (silicon on insulator) material as opposed to a bulk technology. In this case, the good contact draws upon electrons from itself as well as the small S/D region it contacts. If a contact is open, then the electrical node is reduced to the top half of the contact. The difference in capacitance and leakage resistance between the good and bad contact may only be a factor of 2 or 3. As the use of SOI technology increases, and feature size continues to reduce, it is becoming more challenging to detect defects of this type. Therefore, an improved tool and methodology for voltage contrast inspection is desirable.